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:date: 2024.06.04 03:13:50
:_modified: 1970.01.01 00:00:00
:tags: doc,HW
:authors: Gilhad
:summary: Comp24 - documentation part
:title: Comp24 - docs
:nice_title: |logo| %title% |logo|

%HEADER%

Comp24 - System Overview
--------------------------------------------------------------------------------

Comp24 is an HD6309-based 8-bit computer.

It uses two **MC6850 ACIA** for serial output, an **MC6821 PIA** for parallel operations, and an **R6522 VIA** for versatile I/O tasks. 

Additionally, two **Arduino Mega** are integrated: one handles **video** output and **PS/2** keyboard input, while the other manages **SD card** file operations and preloads the "**ROM**" area of RAM during boot. 

Glue logic uses **ATF1504 CLPD** for its pin count. 

Four **32KB SRAM** chips are used.

System Architecture
================================================================================

The system architecture consists of the following main components:

* **HD6309 Processor**: The central processing unit.
* **ATF1504 CPLD**: Manages memory mapping, control signals, and interfacing logic.
* **RAM Chips**: Four 32KB RAM chips (RAM0 to RAM3).
* **74HC245 Bus Transceivers**: Used for address and data bus isolation.
* 2 **Arduino Mega**: Used as sofisticated devices, share RAM2 and RAM3 with CPU
* 2 **MC6850 ACIA**: for two serial outputs
* **MC6821 PIA**: for parallel operations
* **R6522 VIA**: for versatile I/O tasks and clock interrupt.

Memory Mapping and Paging
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Base Memory Mapping
================================================================================

The base memory is used, when no device or overlay is actually mapped on given address

* **RAM0** (32KB): Fixed mapping at address range 0000-7FFF.
* **RAM1** (32KB): Default mapping at address range 8000-FFFF unless overridden by paging.

Overlay Memory Mapping
================================================================================

Overlay may be requested by writing corresponding number to CPLD page register. When acces is granted, 16KB is mapped to 8000-BFFF range.

RAM2 and RAM3: Mapped using the `page register`.

* **RAM2**: Mapped to 8000-BFFF when `page register` is set to `100` (low half) or `101` (high half).
* **RAM3**: Mapped to 8000-BFFF when `page register` is set to `110` (low half) or `111` (high half).

I/O Device Mapping
================================================================================

* **Devices (8 x 16 bytes)**: Mapped at address range C000-C07F.
* **CPLD Registers**:
	* **Page Register**: C080 (R/W)
	* **Status Register**: C081 (R/O)

Control Logic and Signals
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RAM Control
================================================================================

* **RAM0 and RAM1**: Directly connected to CPU bus.
	* **CE**: Decoded by address.
	* **OE and WE**: Qualified by R/W and E signals.

* **RAM2 and RAM3**: Controlled via CPLD and 74HC245 transceivers, or by respective Arduino.
	* **Address Bus (74HC245 x2)**: Direction and enable controlled by CPLD.
	* **Data Bus (74HC245 x1)**: Direction controlled by system R/W signal, enabled by CPLD.
	* **Address Line 14 (addr14)**: Set by CPLD based on requested half (low/high).
	* **Control (CS, OE, WE)**: set by CPLD directly

Arduino Integration
================================================================================

* **Control Lines for CPLD**:
	* **RAMowned**: Indicates RAM ownership (output from CPLD).
	* **RAMwanted**: Indicates RAM request (input to CPLD).
	* **shouldAct**: Indicates if the CPU or Arduino should act on the RAM (output from CPLD).

* **RAM2 or RAM3**:
	* All signal, address and data lines. 

If Arduino "owns" the RAM2 (or RAM3), then Arduino manipulates all pins of the RAM; CPLD and 74HC245 have all associated lines in High-Z state.

If CPU "owns" the RAM2 (or RAM3), then CPLD and 74HC245 manipulates all pins of the RAM; Arduino have all associated lines in High-Z state.


CPLD Registers and Bits
================================================================================

* **Page Register (C080)**:
	* **000**: RAM1 mapped.
	* **100**: RAM2 (low half) mapped.
	* **101**: RAM2 (high half) mapped.
	* **110**: RAM3 (low half) mapped.
	* **111**: RAM3 (high half) mapped.
 
* **Status Register (C081)**:
	* **owned**: Requested page is mapped in for use.
	* **Ard1want**: Arduino 1 requests RAM2.
	* **Ard2want**: Arduino 2 requests RAM3.
	* **toAct1**: CPU should act on RAM2.
	* **toAct2**: CPU should act on RAM3.

Memory Access and Ownership
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Ownership Rules
================================================================================

* **RAM ownership** can change from:
	* None to CPU.
	* CPU to None.
	* None to Arduino.
	* Arduino to None.
* Direct ownership transfer between CPU and Arduino is not allowed.
* Ownership is for full chip - switching low and high half does not change ownership.

Control Signal Management
================================================================================

* When **CPU** owns RAM2/RAM3:
	* Address and data bus transceivers enabled.
	* CE, OE, WE signals, and addr14 are managed by CPLD.
* When **Arduino** owns RAM2/RAM3:
	* Address and data bus transceivers disabled (High-Z state).
	* CE, OE, WE signals, and addr14 from CPLD are set to High-Z.