Comp24
My computer for year 2024
Comp24-CLPD
2024.05.07 21:07:19 end HW Gilhad
  • Adress decoder, with compact devices, paging of RAM, sharing RAM with Arduinos, allow prefill of RAM on boot/reset (so ROM-less)
  • ATF1504AS - 5V, 64 IO pins (+4 JTAG, + PWR & GND (many))
  • JTAG = In System Programming

2   Memory map

  • C???-FFFF ~ 16kB "ROM" + vectors
  • C000-C??? 16B x ?? Devices
  • 8000-BFFF 16kB Paged
  • 0000-7FFF 32kB RAM

3   Idea

This ATF1504 CLPD will be programmed by CUPL code and will serve as "glue logic" for 8bit computer. There will be two main 32kB RAM chips, one connected to bottom half of address space as normal RAM (0000-7FFF). The other will be mapped to top half, but it will be overlayed by other memory mapped devices, as follows: Bottom half of the top memory (8000-BFFF) will be there, until other memory is paged in, and will be there again after other memory is paged out. On bottom of top quarter of memory (C000 ...) will be permanently mapped 8 devices per 16 bytes each and internal registers of this CLPD. The rest will serve as "system ROM" for system services.

4   CUPL

4.1   CUPL code - Header

/* HEADER */
Name     Comp24 ;
PartNo   Glue-001 ;
Date     18/05/2024 ;
Revision 01 ;
Designer Gilhad ;
Company  None ;
Assembly None ;
Location  ;
Device  f1504isptqfp100;

/* Start Here */

/*****************************************************/
/* ATF1504 CUPL Glue logic for Comp24 - first test   */
/*                                                   */
/*                                                   */
/*****************************************************/

4.2   CUPL code - not used Pins (NC, PWR, GND, JTAG)

/* Not connected, power, GND and JTAG */
/*
        Pin 1  = NC;
        Pin 2  = NC;
        Pin 3  = VCC;
        Pin 4  = TDI;
        Pin 5  = NC;
        Pin 7  = NC;
        Pin 11 = GND;
        Pin 15 = TMS;
        Pin 18 = VCC;
        Pin 22 = NC;
        Pin 24 = NC;
        Pin 26 = GND;
        Pin 27 = NC;
        Pin 28 = NC;
        Pin 34 = VCC;
        Pin 38 = GND;
        Pin 39 = VCC;
        Pin 43 = GND;
        Pin 49 = NC;
        Pin 50 = NC;
        Pin 51 = VCC;
        Pin 53 = NC;
        Pin 55 = NC;
        Pin 59 = GND;
        Pin 62 = TCK;
        Pin 66 = VCC;
        Pin 70 = NC;
        Pin 72 = NC;
        Pin 73 = TDO;
        Pin 74 = GND;
        Pin 77 = NC;
        Pin 78 = NC;
        Pin 82 = VCC;
        Pin 86 = GND;
        Pin 91 = VCC;
        Pin 95 = GND;
*/

4.3   CUPL code - Pin assignment (common)

/* Inputs */

Pin 6  = IO_1;
Pin 8  = IO_2;
Pin 9  = IO_3;
Pin 10 = IO_4;
Pin 12 = IO_5;
Pin 13 = IO_6;
Pin 14 = IO_7;
Pin 16 = IO_8;
Pin 17 = IO_9;
Pin 19 = IO_10;
Pin 20 = IO_11;
Pin 21 = IO_12;
Pin 23 = IO_13;
Pin 25 = IO_14;
Pin 29 = IO_15;
Pin 30 = IO_16;
Pin 31 = IO_17;
Pin 32 = IO_18;
Pin 33 = IO_19;
Pin 35 = IO_20;
Pin 36 = IO_21;
Pin 37 = IO_22;
Pin 40 = IO_23;
Pin 41 = IO_24;
Pin 42 = IO_25;
Pin 44 = IO_26;
Pin 45 = IO_27;
Pin 46 = IO_28;
Pin 47 = IO_29;
Pin 48 = IO_30;
Pin 52 = IO_31;
Pin 54 = IO_32;
Pin 56 = IO_33;
Pin 57 = IO_34;
Pin 58 = IO_35;
Pin 60 = IO_36;
Pin 61 = IO_37;
Pin 63 = IO_38;
Pin 64 = IO_39;
Pin 65 = IO_40;
Pin 67 = IO_41;
Pin 68 = IO_42;
Pin 69 = IO_43;
Pin 71 = IO_44;
Pin 75 = IO_45;
Pin 76 = IO_46;
Pin 79 = IO_47;
Pin 80 = IO_48;
Pin 81 = IO_49;
Pin 83 = IO_50;
Pin 84 = IO_51;
Pin 85 = IO_52;
Pin 92 = IO_53;
Pin 93 = IO_54;
Pin 94 = IO_55;
Pin 96 = IO_56;
Pin 97 = IO_57;
Pin 98 = IO_58;
Pin 99 = IO_59;
Pin 100 = IO_60;

/* INPUT ONLY pins */

Pin 87 = xIO_61; /* INPUT/GCLK1 */
Pin 88 = xIO_62; /* INPUT/OE1 - 12V Vpp*/
Pin 89 = xIO_63; /* INPUT/GCLR */
Pin 90 = xIO_64; /* INPUT/OE2/GCLK2 */

4.4   CUPL code - Pin assignment

/* Inputs */

Pin [6,8,9,10,12,13,14,16,17,19,20,21,23,25,29,30]  = [A15..0];
Pin 31 = IO_17;
Pin 32 = IO_18;
Pin 33 = IO_19;
Pin 35 = IO_20;
Pin 36 = IO_21;
Pin 37 = IO_22;
Pin 40 = IO_23;
Pin 41 = IO_24;
Pin 42 = IO_25;
Pin 44 = IO_26;
Pin 45 = IO_27;
Pin 46 = IO_28;
Pin 47 = IO_29;
Pin 48 = IO_30;
Pin 52 = IO_31;
Pin 54 = IO_32;
Pin 56 = IO_33;
Pin 57 = IO_34;
Pin 58 = IO_35;
Pin 60 = IO_36;
Pin 61 = IO_37;
Pin 63 = IO_38;
Pin 64 = IO_39;
Pin 65 = IO_40;
Pin 67 = IO_41;
Pin 68 = IO_42;
Pin 69 = IO_43;
Pin 71 = IO_44;
Pin 75 = IO_45;
Pin 76 = IO_46;
Pin 79 = IO_47;
Pin 80 = IO_48;
Pin 81 = IO_49;
Pin 83 = IO_50;
Pin 84 = IO_51;
Pin 85 = IO_52;
Pin 92 = IO_53;
Pin 93 = IO_54;
Pin 94 = IO_55;
Pin 96 = IO_56;
Pin 97 = IO_57;
Pin 98 = IO_58;
Pin 99 = IO_59;
Pin 100 = IO_60;

/* INPUT ONLY pins */

Pin 87 = xIO_61; /* INPUT/GCLK1 */
Pin 88 = xIO_62; /* INPUT/OE1 - 12V Vpp*/
Pin 89 = xIO_63; /* INPUT/GCLR */
Pin 90 = xIO_64; /* INPUT/OE2/GCLK2 */

4.5   CUPL code - Formulas

cosi = [xIO_61..64]:$ ;
IO_1 = cosi;

chatGPT: Address Decoding with ATF1504 CPLD

The ATF1504 CPLD will be programmed using CUPL code to function as the "glue logic" for an 8-bit computer. This document outlines the memory mapping and address decoding scheme implemented by the CPLD.
Memory Map Overview

The memory map of the 8-bit computer consists of two main 32KB RAM chips, along with memory-mapped devices and system ROM. The address space is divided as follows:

    Lower 32KB RAM (0000-7FFF):
        This segment is dedicated to the first 32KB RAM chip, functioning as regular RAM.

    Upper 32KB Memory (8000-FFFF):
        This segment is divided into several regions with specific purposes:
            Lower half of the upper 32KB (8000-BFFF):
                Initially mapped to the second 32KB RAM chip.
                This region can be temporarily overlaid by other memory-mapped devices. Once these devices are paged out, the RAM will be mapped back.
            Lower quarter of the top 32KB (C000-CFFF):
                Permanently allocated for 8 memory-mapped devices, each occupying 16 bytes.
                Includes internal registers of the CPLD.
            Upper quarter of the top 32KB (D000-FFFF):
                Reserved for system ROM, providing essential system services.

Detailed Memory Mapping

    0000-7FFF: Lower 32KB RAM
        This region is straightforwardly mapped to the first 32KB RAM chip, providing standard read/write operations.

    8000-BFFF: Overlayed Upper 16KB RAM
        This part of the address space is mapped to the second 32KB RAM chip.
        It can be dynamically overlaid by other memory-mapped devices when needed.
        After the temporary memory usage, the RAM mapping is restored.

    C000-CFFF: Memory-Mapped Devices and CPLD Registers
        This 4KB region is allocated for:
            8 memory-mapped devices: Each device occupies a 16-byte block within this range.
            CPLD internal registers: Used for controlling the memory paging and other functions.

    D000-FFFF: System ROM
        The final 12KB of the address space is dedicated to system ROM.
        This ROM contains the firmware and system services necessary for the operation of the computer.

Conclusion

The ATF1504 CPLD efficiently handles the address decoding for the 8-bit computer, ensuring seamless integration of RAM, memory-mapped devices, and system ROM. By carefully mapping the address space, the system maintains flexibility and functionality for various computing tasks.

can you also suggest the corresponding CUPL program? ChatGPT

Certainly! Below is an example CUPL program that corresponds to the address decoding scheme described. This program will set up the ATF1504 CPLD to handle the memory mapping as outlined.

cpld

Name     8BitComputerAddressDecoder;
PartNo   00;
Date     05/18/2024;
Revision 01;
Designer YourName;
Company  YourCompany;
Assembly None;
Location None;
Device   f1504;

 /* Declare the pin names for the address lines, chip select lines, and other control signals */
Pin 1   = A15;
Pin 2   = A14;
Pin 3   = A13;
Pin 4   = A12;
Pin 5   = A11;
Pin 6   = A10;
Pin 7   = A9;
Pin 8   = A8;

Pin 9   = CS_RAM1;  /* Chip Select for Lower 32KB RAM */
Pin 10  = CS_RAM2;  /* Chip Select for Upper 32KB RAM */
Pin 11  = CS_DEV1;  /* Chip Select for Device 1 */
Pin 12  = CS_DEV2;  /* Chip Select for Device 2 */
Pin 13  = CS_DEV3;  /* Chip Select for Device 3 */
Pin 14  = CS_DEV4;  /* Chip Select for Device 4 */
Pin 15  = CS_DEV5;  /* Chip Select for Device 5 */
Pin 16  = CS_DEV6;  /* Chip Select for Device 6 */
Pin 17  = CS_DEV7;  /* Chip Select for Device 7 */
Pin 18  = CS_DEV8;  /* Chip Select for Device 8 */
Pin 19  = CS_ROM;   /* Chip Select for System ROM */

Field Address = [A15..A8];

 /* Address decoding logic */
CS_RAM1 = (Address >= 0x00) & (Address <= 0x7F); /* 0000-7FFF: Lower 32KB RAM */
CS_RAM2 = (Address >= 0x80) & (Address <= 0xBF); /* 8000-BFFF: Upper 16KB RAM */

CS_DEV1 = (Address == 0xC0); /* C000-C00F: Device 1 */
CS_DEV2 = (Address == 0xC1); /* C010-C01F: Device 2 */
CS_DEV3 = (Address == 0xC2); /* C020-C02F: Device 3 */
CS_DEV4 = (Address == 0xC3); /* C030-C03F: Device 4 */
CS_DEV5 = (Address == 0xC4); /* C040-C04F: Device 5 */
CS_DEV6 = (Address == 0xC5); /* C050-C05F: Device 6 */
CS_DEV7 = (Address == 0xC6); /* C060-C06F: Device 7 */
CS_DEV8 = (Address == 0xC7); /* C070-C07F: Device 8 */

CS_ROM = (Address >= 0xD0) & (Address <= 0xFF); /* D000-FFFF: System ROM */

 /* Overlay logic for upper 16KB RAM */
 /* Additional logic can be added here to manage the overlay of memory-mapped devices */

 /* End of file */

Explanation

  • Pin Declarations: The pins are assigned to the address lines (A15 to A8) and the chip select lines for the various RAM, device, and ROM areas.
  • Field Declaration: The Address field groups the address lines for easier manipulation.
  • Address Decoding Logic:
    • CS_RAM1 is active when the address is in the range 0000-7FFF.
    • CS_RAM2 is active when the address is in the range 8000-BFFF.
    • CS_DEV1 to CS_DEV8 are active for specific blocks within the range C000-C0FF.
    • CS_ROM is active when the address is in the range D000-FFFF.
  • Overlay Logic: This is a placeholder for any additional logic needed to manage the overlaying of the RAM with other memory-mapped devices.

You may need to adjust the exact pin numbers and logic according to your specific hardware configuration and requirements.