My computer for year 2024
Comp24 specification
2024.01.22 05:37:29 end doc Gilhad

1   Comp24 specification

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Comp24 is my 8-bit computer for year 2024, so the name. I bought OMEN kilo but its lack of periferials and inability to control communication (like with RTS/CTS) resulted in desire to improve it radically.

  • CPU - HD6309 for now, but later should be possible to use also 6502 and maybe more others
  • Speed - 4MHz for CPU, 115.220 baud for Serial
  • I/O
    • at least 3 Serial ports (with RTS/CTS)
      • PC (debug, upload)
      • PS/2 keyboard+terminal
      • generic use
    • at least 4 Paralel ports (8-bit each)
      • 2 for generic use (and with LED indicators)
      • SPI, I2C (both by bit bang)
      • maybe SD card for filesystem
    • RTC (and time interrupts 100x per sec)
      • date + time
      • debounce
      • alarms
    • beeper
      • maybe with tones?
      • mayne sound card later?
    • video output
    • keyboard
  • Expansions
    • Expanduino or something like that - SD card interface, SPI, I2C and full Arduino connectivity + compatibility
    • RAM only - ATMEGA will Halt 6309 on start and prefill ROM part of RAM (vectors and basic system)
    • Shared RAM - 8kB of RAM will be shared with ATMEGA for fast communication
      • one or more chips, so both computers could run in paralel
        • filesystem transfers
        • videoRAM
        • ...
    • system bus for future expansion
  • Memory
    • 0000-7FFF - 32K RAM (1. UT62256C)
    • 8000-9FFF - 8K bank (shared with ATMEGA)
    • A000-BCFF - 7.5K RAM (A000..Devices) for system (part of 2.UT62256C) (I/O buffers, system variables and such)
    • BE00-BFFF - 16 x 32B - Memory mapped Devices
    • C000-FFFF - 16K "ROM" (part of 2.UT62256C)
  • Memory mapped Devices
    • IO[0..15] x 32 Bytes = 512 Bytes (BE00-BFFF)
      • decoded to 16 lines active LOW
        • each card can/should use only IOxx + A0..A4 + Read + Write (maybe GAL to decode?)
      • BE00-BE1F
      • BE20-BE3F
      • BE40-BE5F
      • BE60-BE7F
      • BE80-BE9F
      • BEA0-BEBF
      • BEC0-BEDF
      • BEE0-BEFF
      • BF00-BF1F
      • BF20-BF3F
      • BF40-BF5F
      • BF60-BF7F
      • BF80-BF9F
      • BFA0-BFBF
      • BFC0-BFDF
      • BFE0-BFFF
    • first address for read is 8-bit ID of device (binary: xxxx xxxx xxx0 0000 address)
      • special signal is generated, so IOxx x IDreq is all needed (and 245 with fixed DIR and set of pull-ups/downs)
    • Serial cards:
      • 0 000 + 0 0001 write = Set and Reset registers for SR pinheader, 0 0001 read = value of SR pinheader (for RTS and such)

2   Shared RAM

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  • 8K RAM at 8000 (from 32K RAM)

  • device with registres
    WANTED_PART             EQU     2
    BANK                    EQU     $BE20
    BANK_STATUS_REG         EQU     BANK+1
    BANK_CONTROL_REG        EQU     BANK+1
    BANK_PART_REG           EQU     BANK+2
    FILE_READ               EQU     12      ; value be decided later
            LDA #WANTED_PART        ; 0..3 for RAM from 32K bank (later maybe more values for ROM, video, etc.)
    CheckLoop1                      ; it may take time
            CMPA BANK_STATUS_REG    ; ?is already mapped? (read reg, containing number of currently mapped part, or #$FF for nothing)
            BEQ AlreadyDone         ; .. if yes, nothing more neaded
            STA BANK_CONTROL_REG    ; .. if no, ask for it
    ;       ...                     ; possibly do some other work
            BRA CheckLoop1          ; and look again
    AlreadyDone                     ; now we have the part accessible
            LDX #$8000              ; the mapped block
            LDA #0                  ; the requested use - 00 none (page is empty, nothing to do), FF none (page is full, do not touch it)
            STA 0,X                 ; set the use at first byte (well, not good example, we should not request it, when we not need it)
    ;       ...                     ; later
            LDA #FILE_READ          ; read file 'FNAME\0' from 'FIRST', 'TOTAL' bytes at max (max 7K or so)
            STA ,X+                 ; store command, move pointer
            LDY #FNAME              ; get address of requested FNAME
            LDA ,Y+                 ; copy byte
            STA ,X+
            BNE FNAMELoop1          ; including zero after end of string
            LDY #$1234              ; from this byte (1234)
            STY ,X++                ; store it
            LDY #$FFFF              ; so much (as much as possible, the limit if less than 2000 anyway)
            STY ,X++                ; store it
            STA ,X+                 ; placeholder for return code (00 = success)
            STY ,X++                ; placeholder for data lenght in case of success
            ;                       ; now X contains position of first byte of (future) result
            LDA #$FF                ; none Part (so take this away and do what you want)
            STA BANK_CONTROL_REG    ; sent it
    ;       ...                     ; later
            LDA #WANTED_PART        ; we want out task processed
            STA BANK_PART_REG       ; request status of WANTED_PART
            LDA BANK_PART_REG       ; 00 part Empty, 01 part under construction (busy), 02 part finished, FF does not exist at all (unknown Part)
            CMPA #01
            BEQ CheckLoop2          ; busy wait, while is there work on the page
            CMPA #02
            BNE FatalError
            LDA #WANTED_PART
            STA BANK_CONTROL_REG    ; request the part
            BNE CheckLoop3          ; wait for it
    ;       Now we have the part mapped, we may check, wheather it is the right request (should be), and how it ended (should have for return code 00 = success and some value in data lenght word, followed by so many bytes from file)
            ; some error handling
    FNAME   FCN     "FILE.TMP"

3   RAM Expansion Card Documentation

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3.1   Overview

The RAM Expansion Card is designed for 8-bit computers, providing an additional 32kB of RAM that can be mapped to an 8kB address space. This documentation outlines the structure, registers, and functionality of the card.

3.2   Technical Specifications

  • Memory Size: 32kB
  • Address Space: 8kB
  • Addresses:
    • Mapped RAM from 8000 to 9FFF
    • Registers from BE20 up

3.3   Registers

Register 0: Expansion Card ID (Read Only)

  • Address: BE20
  • Description: Identifies the expansion card.
  • Access: Read Only

Register 1: Control/Status Register

  • Address: BE21

  • Description: Controls the mapping of RAM to the address space and provides status information.

  • Access: Read/Write

    Control/Status Register Bits:

    • Bits 0-3: RAM Part Selection (Write)
      • 0 to 7: Maps the corresponding RAM part to the address space (8000 to 9FFF).
      • FF: No RAM mapped (default).
    • Bit 7: Busy Flag (Read)
      • 0: RAM part is ready or mapped.
      • 1: RAM part is busy.

Register 2: Query Register

  • Address: BE22

  • Description: Provides the status of the currently requested RAM part.

  • Access: Read

    Query Register Bits:

    • Bits 0-3: Status (Read)
      • 0: RAM part is ready or mapped.
      • 1: RAM part is busy.
      • FF: RAM part does not exist.

3.4   Operation

  • Read Expansion Card ID:
    • Read from BE20 to get the expansion card ID.
  • Control RAM Mapping:
    • Read/Write to BE21 to control RAM mapping.
    • Writing a value from 0 to 7 maps the corresponding RAM part.
    • Writing FF disables RAM mapping.
  • Query RAM Status:
    • Read from BE22 to get the status of the currently requested RAM part.

3.5   Notes

  • When RAM is not mapped in, it is not accessible to the processor, and reads/writes are directed to the underlying system RAM.
  • Changes to RAM mapping in the control register may take some time to be completed.

This documentation provides the technical details for integrating and utilizing the RAM Expansion Card in your 8-bit computer system.