Name ATF1_GLUE;
PartNo 0001;
Date 2026-06-13;
Revision 0.2;
Designer ChatGPT;
Company None ;
Assembly None ;
Location ;
Device f1504isptqfp100;
/*
Skutecna jmena signalu a cisla pinu, pokud je pred jmenem !, je signal aktivni v LOW:
*/
/************************************************************/
/* INPUTS */
/************************************************************/
PIN 6 = CA0;
PIN 8 = CA1;
PIN 9 = CA2;
PIN 10 = CA3;
PIN 12 = CA4;
PIN 13 = CA5;
PIN 14 = CA6;
PIN 16 = CA7;
PIN 17 = CA8;
PIN 19 = CA9;
PIN 20 = CA10;
PIN 21 = CA11;
PIN 23 = CA12;
PIN 25 = CA13;
PIN 29 = CA14;
PIN 30 = CA15;
PIN 31 = Rw;
PIN 32 = !HALT;
PIN 33 = BA;
PIN 35 = !NMI;
PIN 36 = !IRQ;
PIN 37 = !FIRQ;
PIN 40 = !DMA_BREQ;
PIN 41 = MRDY;
PIN 42 = BS;
/*
unused so far
Pin 44 = IO_26;
Pin 45 = IO_27;
Pin 46 = IO_28;
Pin 47 = IO_29;
Pin 48 = IO_30;
Pin 52 = IO_31;
Pin 54 = IO_32;
Pin 56 = IO_33;
Pin 57 = IO_34;
*/
Pin 71 = BootSrc; /* 1=ROM, 0=RAM */
/***** Input Only ****/
/* Pin 85 = IO_52; /* INPUT/GCLK3 */
Pin 87 = E; /* INPUT/GCLK1 */
Pin 88 = xIO_62; /* INPUT/OE1 - 12V Vpp */
Pin 89 = !Reset; /* INPUT/GCLR */
Pin 90 = Q; /* INPUT/OE2/GCLK2 */
/************************************************************/
/* OUTPUTS */
/************************************************************/
Pin 69 = RomMapped;
Pin 75 = !ROM;
PIN 76 = !Dev_Sel_7;
PIN 79 = !Dev_Sel_6;
PIN 80 = !Dev_Sel_5;
PIN 81 = !Dev_Sel_4;
PIN 83 = !Dev_Sel_3;
PIN 84 = !Dev_Sel_2;
PIN 92 = !Dev_Sel_1;
PIN 93 = !RAM;
PIN 94 = !Write;
PIN 96 = !Read;
PIN 97 = MR3;
PIN 98 = MR2;
PIN 99 = MR1;
PIN 100 = MR0;
/************************************************************/
/* BIDIRECTIONAL (data) */
/************************************************************/
Pin [58,60,61,63, 64,65,67,68] = [D0..7];
/*
Pin 58 = IO_35;
Pin 60 = IO_36;
Pin 61 = IO_37;
Pin 63 = IO_38;
Pin 64 = IO_39;
Pin 65 = IO_40;
Pin 67 = IO_41;
Pin 68 = IO_42;
*/
/************************************************************/
/* vytazeni vnitrnich vyrazu pro testy */
/************************************************************/
/* {{{ pin numbers
***** PWR, NC, JTAG *****
Pin 1 = NC;
Pin 2 = NC;
Pin 3 = VCC;
Pin 4 = TDI;
Pin 5 = NC;
Pin 7 = NC;
Pin 11 = GND;
Pin 15 = TMS;
Pin 18 = VCC;
Pin 22 = NC;
Pin 24 = NC;
Pin 26 = GND;
Pin 27 = NC;
Pin 28 = NC;
Pin 34 = VCC;
Pin 38 = GND;
Pin 39 = VCC;
Pin 43 = GND;
Pin 49 = NC;
Pin 50 = NC;
Pin 51 = VCC;
Pin 53 = NC;
Pin 55 = NC;
Pin 59 = GND;
Pin 62 = TCK;
Pin 66 = VCC;
Pin 70 = NC;
Pin 72 = NC;
Pin 73 = TDO;
Pin 74 = GND;
Pin 77 = NC;
Pin 78 = NC;
Pin 82 = VCC;
Pin 86 = GND;
Pin 91 = VCC;
Pin 95 = GND;
***** I/O pins *****
Pin 6 = IO_1;
Pin 8 = IO_2;
Pin 9 = IO_3;
Pin 10 = IO_4;
Pin 12 = IO_5;
Pin 13 = IO_6;
Pin 14 = IO_7;
Pin 16 = IO_8;
Pin 17 = IO_9;
Pin 19 = IO_10;
Pin 20 = IO_11;
Pin 21 = IO_12;
Pin 23 = IO_13;
Pin 25 = IO_14;
Pin 29 = IO_15;
Pin 30 = IO_16;
Pin 31 = IO_17;
Pin 32 = IO_18;
Pin 33 = IO_19;
Pin 35 = IO_20;
Pin 36 = IO_21;
Pin 37 = IO_22;
Pin 40 = IO_23;
Pin 41 = IO_24;
Pin 42 = IO_25;
Pin 44 = IO_26;
Pin 45 = IO_27;
Pin 46 = IO_28;
Pin 47 = IO_29;
Pin 48 = IO_30;
Pin 52 = IO_31;
Pin 54 = IO_32;
Pin 56 = IO_33;
Pin 57 = IO_34;
Pin 58 = IO_35;
Pin 60 = IO_36;
Pin 61 = IO_37;
Pin 63 = IO_38;
Pin 64 = IO_39;
Pin 65 = IO_40;
Pin 67 = IO_41;
Pin 68 = IO_42;
Pin 69 = IO_43;
Pin 71 = IO_44;
Pin 75 = IO_45;
Pin 76 = IO_46;
Pin 79 = IO_47;
Pin 80 = IO_48;
Pin 81 = IO_49;
Pin 83 = IO_50;
Pin 84 = IO_51;
Pin 92 = IO_53;
Pin 93 = IO_54;
Pin 94 = IO_55;
Pin 96 = IO_56;
Pin 97 = IO_57;
Pin 98 = IO_58;
Pin 99 = IO_59;
Pin 100 = IO_60;
***** Input Only ****
Pin 85 = IO_52; /* INPUT/GCLK3 /
Pin 87 = xIO_61; /* INPUT/GCLK1 /
Pin 88 = xIO_62; /* INPUT/OE1 - 12V Vpp/
Pin 89 = xIO_63; /* INPUT/GCLR /
Pin 90 = xIO_64; /* INPUT/OE2/GCLK2 /
}}} */
/************************************************************/
/* REG7 ROM_SIZE */
/************************************************************/
NODE [ROM_SIZE2..0];
FIELD ROM_SIZE = [ROM_SIZE2..0];
/*
4+ = vypnuto
3 = 4k
2 = 8k
1 = 16k
0 = 24.75 kB
*/
/************************************************************/
FIELD CA = [CA15..CA0];
/************************************************************/
/* ADDRESS DECODE */
/************************************************************/
NATIVE_RAM_LO = CA:[0000..7FFF];
EMS1_WINDOW = CA:[8000..8FFF];
EMS2_WINDOW = CA:[9000..9FFF];
/* ATF2 registry */
REG0 = (CA:A000); /* EMS1_PAGE */
REG1 = (CA:A001); /* EMS1_STATUS */
REG2 = (CA:A002); /* EMS2_PAGE */
REG3 = (CA:A003); /* EMS2_STATUS */
REG4 = (CA:A004); /* CHIPA_STATUS */
REG5 = (CA:A005); /* CHIPB_STATUS */
REG_MIRROR = CA:[A006..A01F];
/* nasleduji ATF1 registry */
REG6 = (CA:A006); /* ROM_STATUS */
REG7 = (CA:A007); /* ROM_SIZE */
DEVICE_AREA = CA:[A020..A0FF];
ROM_24K = CA:[A100..FFFF];
ROM_16K = CA:[C000..FFFF];
ROM_8K = CA:[E000..FFFF];
ROM_4K = CA:[F000..FFFF];
ROM_AREA =
RomMapped &
(
((ROM_SIZE:0) & ROM_24K)
# ((ROM_SIZE:1) & ROM_16K)
# ((ROM_SIZE:2) & ROM_8K)
# ((ROM_SIZE:3) & ROM_4K)
/* ROM_SIZE 4+ == zadna ROM */
)
;
NATIVE_RAM_HI = ROM_24K & !ROM_AREA;
/************************************************************/
/* MEMORY REGION BUS */
/************************************************************/
MR0 =
EMS1_WINDOW
# ROM_AREA
# REG1
# REG3
# REG5
# REG_MIRROR;
MR1 =
EMS2_WINDOW
# ROM_AREA
# DEVICE_AREA
# REG2
# REG3
# REG_MIRROR;
MR2 =
DEVICE_AREA
# REG4
# REG5
# REG_MIRROR;
MR3 =
REG0
# REG1
# REG2
# REG3
# REG4
# REG5
# REG_MIRROR;
/*
NATIVE_RAM_LO MR = 0; 0000
NATIVE_RAM_HI MR = 0; 0000
EMS1_WINDOW MR = 1; 0001
EMS2_WINDOW MR = 2; 0010
REG0 MR = 8; 1000
REG1 MR = 9; 1001
REG2 MR = 10; 1010
REG3 MR = 11; 1011
REG4 MR = 12; 1100
REG5 MR = 13; 1101
REG_MIRROR MR = 15; 1111
DEVICE_AREA MR = 4; 0100
ROM_AREA MR = 3; 0011
*/
/************************************************************/
/* READ / WRITE */
/************************************************************/
Read = E & Rw;
Write = E & !Rw;
/************************************************************/
/* DEVICE SELECTS */
/************************************************************/
/*
* EMS windows:
* ATF1 releases DEV0
* ATF2 drives DEV0
*/
RAM = NATIVE_RAM_LO
# NATIVE_RAM_HI
;
ROM = ROM_AREA;
EMS_WINDOW = EMS1_WINDOW # EMS2_WINDOW;
RAM.OE = !EMS_WINDOW & !BA; /* managed by ATF2 */
ROM.OE = !EMS_WINDOW & !BA; /* managed by ATF2 */
/************************************************************/
/* DEVICE BLOCK */
/************************************************************/
Dev_Sel_1 = CA:[A020..A03F] & !BA;
Dev_Sel_2 = CA:[A040..A05F] & !BA;
Dev_Sel_3 = CA:[A060..A07F] & !BA;
Dev_Sel_4 = CA:[A080..A09F] & !BA;
Dev_Sel_5 = CA:[A0A0..A0BF] & !BA;
Dev_Sel_6 = CA:[A0C0..A0DF] & !BA;
Dev_Sel_7 = CA:[A0E0..A0FF] & !BA;
/************************************************************/
/* ATF1 Registers Write */
/************************************************************/
/************************************************************/
/* REG6 ROM_STATUS */
/************************************************************/
/* RomMapped se pri resetu nastavi na BootSrc,
pri zapisu zmeni hodnotu na zapsanou */
/*
RomMapped.d =
Reset & BootSrc
# !Reset & D0;
RomMapped.CK = E;
RomMapped.CE = Reset
# REG6 & !Rw;
*/
RomMapped.d = D0;
RomMapped.CK = !Q;
RomMapped.AR = Reset & !BootSrc;
RomMapped.AP = Reset & BootSrc;
RomMapped.CE = REG6 & !Rw & !BA;
/************************************************************/
/* REG7 ROM_SIZE */
/************************************************************/
ROM_SIZE.d=[D2..D0];
ROM_SIZE.CK=!Q;
ROM_SIZE.AR=Reset;
ROM_SIZE.CE = REG7 & !Rw & !BA;
/************************************************************/
/* ATF1 Registers Read */
/************************************************************/
[D7..D0].OE = E & Rw & ( REG6 # REG7 ) & !BA; /* write full D */
[D7..D3] = E & !E; /* 0 for unused */
[D2] = REG7 & ROM_SIZE2
# REG6 & !REG6; /* 0 for REG6 */
[D1] = REG7 & ROM_SIZE1
# REG6 & BootSrc;
[D0] = REG7 & ROM_SIZE0
# REG6 & RomMapped;
CPLD ATF1