2.1   CPLD

• ATF1504AS: 64 macrocells, 64 I/O for use

• System bus:

  • !Reset: global Input pin, sets internal values to zero (but other functions are still enabled)
  • !HALT: Output pin, pullup, connected to CPU, either driven LOW or 3stated (HighZ, normal state) - reflects A_HALT state
  • [A0..15]: Input bus, used for address decoding and internal registers access
  • [D0..7]: I/O bus, used for internal registers access

• Arduino part:

  • !A_HALT: Input pin, pulldown, connected to Arduino0, after reset LOW, until Arduino0 set it HIGH
  • A{0,1}_ToAct: output, if HIGH, the coresponding Arduino should process its RAM{2,3}, set by CPU releasing the RAM, reset by Arduino releasing the RAM
  • A{0,1}_WantRAM: input, if HIGH, the coresponding Arduino wants to own its RAM{2,3}, if LOW, Arduino release the RAM
  • A{0,1}_OwnRAM: output, if HIGH, the coresponding Arduino have RAM granted, set by CPU releasing the RAM, reset by Arduino releasing the RAM

• RAM{2,3} part: active only if CPU owns the RAM, otherwise 3stated (HighZ)

  • _CE: if CPU owns the RAM. Also sets address 245' OE and dir from CPU
  • _OE: if E and Rw are active. Also sets data 245' OE and dir to CPU
  • _WE: if E is active and Rw is not. Also sets data 245' OE and dir from CPU

• gate{2,3} part:

  • _DATA:

  • _ADDRESS:

    • _DIR: 0=from CPU, 1=to CPU
    • _OE:

2.2   Arduino0

• System bus:

  • E: R/O, for timing
  • Rw: R/W, for HALT time

2.3   Boot sequence

• Power on / reset:

  • Reset line is hold down, then (relatively) slowly rises up

    • Arduino{0,1} is reseted, all pins are input (HighZ), setup() is initiated

    • CPLD have all registers zeroed, otherwise works

      • RAM{2,3} are not owned
      • A_HALT is propagated to HALT

    • CPU is HALTed, before Reset rises high enought, then the internal reset starts (in halted state)

• starting:

  • Arduino0:

    • keeps A_HALT down
    • keep system Rw high (Read)
    • propagates Address Buss to CPU, Data Bus is 3stated(HighZ)
    • reads configuration from SD (or default from Flash)

    • writes "ROM" content into RAM:

      • sets Address lines, set Data lines, set Rw low (write) and opens Data Bus to CPU, waits at least one full E cycle, then sets Rw high(Read) and then sets Data Bus 3stated(HighZ) (as the data are the same for write and then read, no conflict occures), then repeat for next byte

    • 3states Address Bus and Rw
    • push A_HALT high

  • CPU:

    • after HALT rises, continue Reset by reading FFFE vector from "ROM"

      • initialise all devices
      • starts system

     +----- 3k3 --------------------+-- Halt HD6309
     |                              |
     |                              +----------------- Halt CPLD
     |
     |
     |
+5V -+---- 10k --+-----+-----+------+-- Reset HD6309
                 |     |     |      |
                 |     |     |      +----------------- Reset CPLD
                 |     |     |      |
                1µF    1M  RESET    +-------------------------------------- Reset Arduino1
                 |     |   BUTTON   |
                 |     |     |      +-------------------------------------- Reset Arduino2
                 |     |     |
GND -------------+-----+-----+

+5V -----------+
               |
              100k
               |
CPLD A_Halt ---+----------+------ A_Halt Arduino1
                          |
                         3k3
                          |
GND ----------------------+------ GND Arduino

+5V ----+----- 10kΩ ------+-------+-------- RESET (HD6309)
        |                 |       |
        |                 |       |
        |                 |       |
      10µF               RESET    |
        |                BUTTON   |
        |                 |       |
       GND               GND      |
                                  |
A_HALT (Arduino) ------+----------|--------> HALT (HD6309)
                       |          |
                       |          |
                     CPLD        CPLD
                     Logic       Logic
                   for HALT   for Bus Control

PIN     = [A0..A15];    /*  I; active high      CPU address bus */
PIN     = [D0..A7];     /*  I; active high      CPU data bus */
PIN     = E;            /*  I; active high      E CPU.34                System clock */
PIN     = Rw;           /*  I; active high      R/~{W} CPU.32   1=Read; 0=Write */

PIN     = !RAM0_CS;     /*  O; active low       Chip select for RAM0 */
PIN     = !RAM1_CS;     /*  O; active low       Chip select for RAM1 */
PIN     = !RAM01_OE;    /*  O; active low       Read qualified by E     For RAM0, RAM1 */
PIN     = !RAM01_WE;    /*  O; active low       Write qualified by E    For RAM0, RAM1 */

RAM01_OE        = E & Rw;
RAM01_WE        = E & !Rw;

PIN     = !RAM2_CS;     /*  O3; active low      Chip select for RAM2 */
PIN     = !RAM3_CS;     /*  O3; active low      Chip select for RAM3 */

2.4   Junk to be deleted later

Name     Comp24_CPLD;
PartNo   ATF1504;
Date     2024-06-04;
Revision 1;
Designer ChatGPT;
Company  OpenAI;
Assembly None;
Location None;

Device   g22v10;

PIN 1   = CPU_A15;
PIN 2   = CPU_A14;
PIN 3   = CPU_A13;
PIN 4   = CPU_A12;
PIN 5   = CPU_A11;
PIN 6   = CPU_A10;
PIN 7   = CPU_A9;
PIN 8   = CPU_A8;
PIN 9   = CPU_A7;
PIN 10  = CPU_A6;
PIN 11  = CPU_A5;
PIN 12  = CPU_A4;
PIN 13  = CPU_A3;
PIN 14  = CPU_A2;
PIN 15  = CPU_A1;
PIN 16  = CPU_A0;

PIN 17  = CPU_R_W;
PIN 18  = CPU_E;
PIN 19  = CPU_CS;
PIN 20  = RAM_CE;
PIN 21  = RAM_OE;
PIN 22  = RAM_WE;
PIN 23  = ADDR14;
PIN 24  = PAGE_REG;
PIN 25  = STATUS_REG;

PIN 26  = RAM2_CE;
PIN 27  = RAM3_CE;

PIN 28  = RAMowned;
PIN 29  = RAMwanted;
PIN 30  = shouldAct;

PIN 31  = VCC;
PIN 32  = GND;

// Signals for Arduino integration
PIN 33  = Ard1want;
PIN 34  = Ard2want;
PIN 35  = toAct1;
PIN 36  = toAct2;

Field PAGE_REG_FIELD = [PAGE_REG];

// Page Register Values
#define PAGE_RAM1     0b000
#define PAGE_RAM2_L   0b100
#define PAGE_RAM2_H   0b101
#define PAGE_RAM3_L   0b110
#define PAGE_RAM3_H   0b111

// Address Range Definitions
#define ADDR_RANGE_RAM0_START 0x0000
#define ADDR_RANGE_RAM0_END   0x7FFF
#define ADDR_RANGE_RAM1_START 0x8000
#define ADDR_RANGE_RAM1_END   0xFFFF
#define ADDR_RANGE_IO_START   0xC000
#define ADDR_RANGE_IO_END     0xC07F
#define ADDR_RANGE_CPLD_START 0xC080
#define ADDR_RANGE_CPLD_END   0xC081

// Control Logic
RAM_CE = !CPU_CS & (CPU_A15 & CPU_A14 & CPU_A13 & CPU_A12); // Control enable logic
RAM_OE = !CPU_R_W & CPU_E;  // Output enable logic
RAM_WE = CPU_R_W & CPU_E;   // Write enable logic

// Address Line 14 (addr14) Control
ADDR14 = PAGE_REG_FIELD[0];

// RAM Chip Select based on Page Register
RAM2_CE = (PAGE_REG_FIELD == PAGE_RAM2_L) | (PAGE_REG_FIELD == PAGE_RAM2_H);
RAM3_CE = (PAGE_REG_FIELD == PAGE_RAM3_L) | (PAGE_REG_FIELD == PAGE_RAM3_H);

// Status Register Bits
owned = RAMowned;
Ard1want = RAMwanted & (PAGE_REG_FIELD == PAGE_RAM2_L | PAGE_REG_FIELD == PAGE_RAM2_H);
Ard2want = RAMwanted & (PAGE_REG_FIELD == PAGE_RAM3_L | PAGE_REG_FIELD == PAGE_RAM3_H);
toAct1 = shouldAct & (PAGE_REG_FIELD == PAGE_RAM2_L | PAGE_REG_FIELD == PAGE_RAM2_H);
toAct2 = shouldAct & (PAGE_REG_FIELD == PAGE_RAM3_L | PAGE_REG_FIELD == PAGE_RAM3_H);

// Page Register Logic
FIELD PAGE_REG = [CPU_A0, CPU_A1, CPU_A2];
PAGE_REG = CPU_R_W & CPU_CS & (CPU_A15 & CPU_A14 & CPU_A13 & CPU_A12);

// Status Register Logic
STATUS_REG = CPU_R_W & CPU_CS & (CPU_A15 & CPU_A14 & CPU_A13 & CPU_A12);
STATUS_REG[0] = owned;
STATUS_REG[1] = Ard1want;
STATUS_REG[2] = Ard2want;
STATUS_REG[3] = toAct1;
STATUS_REG[4] = toAct2;

END;